| EP0_TX_MAX_P_REG | 0x0100 | 16 | RW | 0 | Maximum packet size for host transmit
endpoint0. |
| EP0_TX_CSR_REG | 0x0102 | 16 | R | 0 | Provides control and status bits for transmit endpoint0. |
| EP0_RX_MAX_P_REG | 0x0104 | 16 | RW | 0 | Defines the maximum amount of data that can be transferred through receive endpoint0 in a single operation. |
| EP0_RX_CSR_REG | 0x0106 | 16 | R | 0 | Provides control and status bits for transfers through the receive endpoint0. |
| EP0_RX_COUNT_REG | 0x0108 | 16 | R | 0 | Holds the number of data bytes in the packet currently in line to be read from the endpoint0 receive FIFO. If the packet was transmitted as multiple bulk packets, the number given will be for the combined packet. |
| EP0_TX_TYPE_REG | 0x010A | 8 | W | 0 | Reads the number of bytes from peripheral endpoint0 transmit FIFO |
| EP0_TX_INTERVAL_REG | 0x010B | 8 | RW | 0 | Sets the polling interval for interrupt/ISOC transactions or the NAK response timeout on bulk transactions for host transmit endpoint0. |
| EP0_RX_TYPE_REG | 0x010C | 8 | RW | 0 | Sets the transaction protocol, speed, and peripheral endpoint number for the host receive endpoint0. |
| EP0_RX_INTERVAL_REG | 0x010D | 8 | RW | 0 | Sets the polling interval for interrupt/ISOC transactions or the NAK response timeout on bulk transactions for host receive endpoint0. |
| EP0_FIFO_SIZE_REG | 0x010E | 8 | R | — | Returns the configured size of the endpoint0 receive FIFO and transmit FIFOs. |
