9.3.10.4 Endpoint3 Control and Status Registers

Table 9-85. Endpoint3 Control and Status Registers
Register NameAddress Offset from 0x40043000WidthR/W TypeReset ValueDescription
EP3_TX_MAX_P_REG0x013016RW0Maximum packet size for host transmit endpoint3.
EP3_TX_CSR_REG0x013216R0Provides control and status bits for transmit endpoint3.
EP3_RX_MAX_P_REG0x013416RW0Defines the maximum amount of data that can be transferred through receive endpoint3 in a single operation.
EP3_RX_CSR_REG0x013616R0Provides control and status bits for transfers through the receive endpoint3.
EP3_RX_COUNT_REG0x013816R0Holds the number of data bytes in the packet currently in line to be read from the endpoint3 receive FIFO. If the packet is transmitted as multiple bulk packets, the number given will be for the combined packet.
EP3_TX_TYPE_REG0x013A8W0Reads the number of bytes from peripheral endpoint3 transmit FIFO.
EP3_TX_INTERVAL_REG0x013B8RW0Sets the polling interval for interrupt/ISOC transactions or the NAK response timeout on bulk transactions for host transmit endpoint3.
EP3_RX_TYPE_REG0x013C8RW0Sets the transaction protocol, speed, and peripheral endpoint number for the host receive endpoint3.
EP3_RX_INTERVAL_REG0x013D8RW0Sets the polling interval for interrupt/ISOC transactions or the NAK response timeout on bulk transactions for host receive endpoint3.
EP3_FIFO_SIZE_REG0x013E8RReturns the configured size of the endpoint3 receive FIFO and transmit FIFOs.