| EP2_TX_MAX_P_REG | 0x0120 | 16 | RW | 0 | Maximum packet size for host transmit endpoint2. |
| EP2_TX_CSR_REG | 0x0122 | 16 | R | 0 | Provides control and status bits for transmit endpoint2. |
| EP2_RX_MAX_P_REG | 0x0124 | 16 | RW | 0 | Defines the maximum amount of data that can be transferred through receive endpoint2 in a single operation. |
| EP2_RX_CSR_REG | 0x0126 | 16 | R | 0 | Provides control and status bits for transfers through the receive endpoint2. |
| EP2_RX_COUNT_REG | 0x0128 | 16 | R | 0 | Holds the number of data bytes in the packet currently in line to be read from the endpoint2 receive FIFO. If the packet is transmitted as multiple bulk packets, the number given will be for the combined packet. |
| EP2_TX_TYPE_REG | 0x012A | 8 | W | 0 | Reads the number of bytes from peripheral endpoint2 transmit FIFO. |
| EP2_TX_INTERVAL_REG | 0x012B | 8 | RW | 0 | Sets the polling interval for interrupt/ISOC transactions or the NAK response timeout on bulk transactions for host transmit endpoint2. |
| EP2_RX_TYPE_REG | 0x012C | 8 | RW | 0 | Sets the transaction protocol, speed, and peripheral endpoint number for the host receive endpoint2. |
| EP2_RX_INTERVAL_REG | 0x012D | 8 | RW | 0 | Sets the polling interval for interrupt/ISOC transactions or the NAK response timeout on bulk transactions for host receive endpoint2. |
| EP2_FIFO_SIZE_REG | 0x012E | 8 | R | — | Returns the configured size of the endpoint2 receive FIFO and transmit FIFOs. |
