| Reference Document | New section |
| Configuration Summary | Updated Table 1-1 |
| Block Diagram | Updated Figure 1-1 |
| Package and Pinout | Updated Table 1-3 |
| DMA Controller (XDMAC) |
Updated Figure 2-8
|
| Overview | Updated Power
Supplies |
| Real-Time Clock (RTC) |
All occurrences of Persian mode deleted
Updated Waveform Generation, Figure 4-35, RTC Accurate Clock Calibration
RTC_MR: index 1 now ‘reserved’; UTC description updated
RTC_SR: updated reset value
|
| Power Management Controller (PMC) |
Throughout: changed “FSTP” to “WIP”
Updated Main Crystal Oscillator Failure Detection
|
| External Bus Interface (EBI) | Added whole chapter |
| DDR-SDRAM Controller (MPDDRC) |
DDR3-SDRAM/DDR3L-SDRAM Initialization: corrected DDR3(L)-SDRAM
value
|
| OTP Memory Controller (OTPC) |
Updated Power Management
|
| LCD Controller (LCDC) | Updated Embedded
Characteristics, Functional
Description LCDC_LCDISR: updated WP description |
| Display Serial Interface (DSI) |
Offsets 0x000000E0–0x000000E8 and 0x000000F8 now ‘reserved’
DSI_INT_FORCE0, DSI_INT_FORCE1: access now Write-only
|
| CSI-2 Demultiplexer Controller (CSI2DC) |
CSI2DC_SSPISR, CSI2DC_GSPISR, CSI2DC_GLPISR, CSI2DC_IDSISR, CSI2DC_DPISR, CSI2DC_VPISR: updated bit descriptions
|
| Image Sensor Controller (ISC) |
Added section Scaler Function
ISC_INTEN, ISC_INTDIS, ISC_INTMASK, ISC_INTSR: added WPE
|
| Inter-IC Sound Multi-Channel Controller (I2SMCC) |
Updated Common Registers
TDM
Reception and Transmission Sequence: added note
I2SMCC_MRA: updated TDMFS description
I2SMCC_MRB: updated I2SLINESIZE description
I2SMCC_ISRA: updated RXLRDYx and TXRRDYx descriptions
|
| Synchronous Serial Controller (SSC) |
Updated Embedded Characteristics
|
| Ethernet MAC (GMAC) |
Updated Embedded Characteristics, GMAC
Connections to PHY in Different Modes, Media
Access Controller, Jumbo
Frames, PHY Interface
GMAC_EMAC_SCR2_RATE_LIMIT1: added register at offset 0x1B44
GMAC_EMAC_DCFGR: FBLDO now at index [4:0]
GMAC_RJFML: updated reset value
GMAC_ISR, GMAC_IER, GMAC_IDR, GMAC_IMR: corrected offsets of TXLCK and RXLCK
GMAC_DCFGR: corrected offset of CRCERRREP
GMAC_RX_WATERMARK, GMAC_EMAC_RX_WATERMARK, GMAC_TQSA, GMAC_EMAC_TQSA, GMAC_SCR2_RATE_STATUS, GMAC_EMAC_TSCTL, GMAC_EMAC_TQBWRL, GMAC_EMAC_ENST_CR, GMAC_EMAC_SCR2_RATE_STATUS, GMAC_NCFGR, GMAC_EMAC_NCFGR: updated bit descriptions
GMAC_FRER_STAT_Bx, GMAC_EMAC_FRER_STAT1_B, GMAC_EMAC_FRER_STAT2_B: bits 25:24 now ‘reserved’
GMAC_SCR2_RATE_LIMITx, GMAC_EMAC_ENST_ON, GMAC_EMAC_ENST_START, GMAC_EMAC_ENST_OFF, GMAC_FRER_CTRL_Ax, GMAC_FRER_CTRL_Bx, GMAC_FRER_STAT_Ax, GMAC_FRER_STAT_Bx: modified index range of registers
|
| Flexible Serial Communication Controller (FLEXCOM) |
Updated I/O Lines Description, Baud Rate in Synchronous Mode
FLEX_TWI_SR (DEFAULT_MODE), FLEX_TWI_SR (FIFO_ENABLED): index 17 now ‘reserved’
|
| Timer Counter (TC) |
Updated Block Diagram
TC_BMR: updated TCxXCxS descriptions
|
| Electrical Characteristics |
Updated Table 10-33, Table 10-15, Digital Peripheral Characteristics
System
Power Consumption in Applicative Use Cases: updated Table 10-63
Operation and Power Consumption in Low-Power Modes: updated Table 10-64
|
| Ordering Information | Updated ordering codes |
