5.5.35 DSI Reset and PLL Control Register
| Name: | DSI_DPHY_RSTZ |
| Offset: | 0xA0 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DPHY_FORCEPLL | DPHY_ENABLECLK | DPHY_RSTZ | DPHY_SHUTDOWNZ | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
Bit 3 – DPHY_FORCEPLL D-PHY Force PLL Enable
| Value | Description |
|---|---|
| 0 | Disables the D-PHY PLL when the D-PHY is in ULPS. |
| 1 | Enables the D-PHY PLL when the D-PHY is in ULPS. |
Bit 2 – DPHY_ENABLECLK D-PHY Enable Clock Lane
| Value | Description |
|---|---|
| 0 | Disables the D-PHY clock lane module. |
| 1 | Enables the D-PHY clock lane module. |
Bit 1 – DPHY_RSTZ D-PHY Reset Disable
| Value | Description |
|---|---|
| 0 | Places the digital section of the D-PHY in the reset state. |
| 1 | Allows the digital section of the D-PHY to leave the reset state. |
Bit 0 – DPHY_SHUTDOWNZ D-PHY Shutdown Disable
| Value | Description |
|---|---|
| 0 | Places the complete D-PHY macro in power-down state. |
| 1 | Allow the complete D-PHY macro to leave power-down state. |