5.5.36 DSI D-PHY Interface Configuration Register
| Name: | DSI_DPHY_IF_CFG |
| Offset: | 0xA4 |
| Reset: | 0x00000003 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| PHY_STOP_WAIT_TIME[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| N_LANES[1:0] | |||||||||
| Access | R/W | R/W | |||||||
| Reset | 1 | 1 | |||||||
Bits 15:8 – PHY_STOP_WAIT_TIME[7:0] D-PHY Stop State Wait Time
Configures the minimum wait period to request a high-speed transmission after the Stop state.
Bits 1:0 – N_LANES[1:0] Number of Active Data Lanes
| Value | Description |
|---|---|
| 0 | One data lane (lane 0) |
| 1 | Two data lanes (lanes 0 and 1) |
| 2 | Three data lanes (lanes 0, 1, and 2) |
| 3 | Four data lanes (lanes 0, 1, 2, and 3) |