The following configuration values are valid for all listed bit names of this register:
0: The corresponding interrupt source is masked.
1: The corresponding interrupt source is activated.
Name:
DSI_INT_MSK1
Offset:
0xC8
Reset:
0x00000000
Property:
Read/Write
Bit
31
30
29
28
27
26
25
24
Access
Reset
Bit
23
22
21
20
19
18
17
16
DPI_BUFF_PLD_UNDER
Access
R/W
Reset
0
Bit
15
14
13
12
11
10
9
8
GEN_PLD_RECEV_ERR
GEN_PLD_RD_ERR
GEN_PLD_SEND_ERR
GEN_PLD_WR_ERR
GEN_CMD_WR_ERR
Access
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
DPI_PLD_WR_ERR
EOTP_ERR
PKT_SIZE_ERR
CRC_ERR
ECC_MULTI_ERR
ECC_SINGLE_ERR
TO_LP_RX
TO_HS_TX
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit 19 – DPI_BUFF_PLD_UNDER Input Video Interface Payload Buffer Underflow
Mask
Bit 12 – GEN_PLD_RECEV_ERR Generic Interface Payload Receive Error Mask
Bit 11 – GEN_PLD_RD_ERR Generic Interface Payload Read Error Mask
Bit 10 – GEN_PLD_SEND_ERR Generic Interface Payload Send Error Mask
Bit 9 – GEN_PLD_WR_ERR Generic Interface Payload Write Error Mask
Bit 8 – GEN_CMD_WR_ERR Generic Interface Command Write Error Mask
Bit 7 – DPI_PLD_WR_ERR Input Video Payload Write Error Mask
Bit 6 – EOTP_ERR End Of Transmission Packet Error Mask
Bit 5 – PKT_SIZE_ERR Packet Size Error Mask
Bit 4 – CRC_ERR CRC Error Mask
Bit 3 – ECC_MULTI_ERR ECC Multiple Error Mask
Bit 2 – ECC_SINGLE_ERR ECC Single Error Mask
Bit 1 – TO_LP_RX Timeout Low-Power Reception Mask
Bit 0 – TO_HS_TX Timeout High-Speed Transmission Mask
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
