5.5.32 DSI Clock Lane Control Register
| Name: | DSI_LPCLK_CTRL |
| Offset: | 0x94 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| AUTO_CLKLANE_CTRL | PHY_TXREQUESTCLKHS | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
Bit 1 – AUTO_CLKLANE_CTRL Automatic Clock Lane Control
| Value | Description |
|---|---|
| 0 | Disables the automatic mechanism to stop providing the clock in the clock lane when time allows. |
| 1 | Enables the automatic mechanism to stop providing clock in the clock lane when time allows. |
Bit 0 – PHY_TXREQUESTCLKHS D-PHY High-Speed Transmission Request
| Value | Description |
|---|---|
| 0 | Disables High-Speed mode transmission request on clock lane. |
| 1 | Enables High-Speed mode transmission request on clock lane. |