5.5.33 DSI Clock Lane Switch Mode Timing Configuration Register
| Name: | DSI_DPHY_TMR_LPCLK_CFG |
| Offset: | 0x98 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| PHY_CLKHS2LP_TIME[9:8] | |||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 | |||||||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| PHY_CLKHS2LP_TIME[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| PHY_CLKLP2HS_TIME[9:8] | |||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 | |||||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PHY_CLKLP2HS_TIME[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 25:16 – PHY_CLKHS2LP_TIME[9:0] D-PHY Clock High-Speed to Low-Power Time
Configures the maximum time that the D-PHY clock lane takes to go from high-speed to low-power transmission measured in lane byte clock cycles.
Bits 9:0 – PHY_CLKLP2HS_TIME[9:0] D-PHY Clock Low-Power to High-Speed Time
Configures the maximum time that the D-PHY clock lane takes to go from low-power to high-speed transmission measured in lane byte clock cycles.