5.5.43 DSI Interrupt Status Register 1
| Name: | DSI_INT_ST1 |
| Offset: | 0xC0 |
| Reset: | 0x00000000 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| DPI_BUFF_PLD_UNDER | |||||||||
| Access | R | ||||||||
| Reset | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| GEN_PLD_RECEV_ERR | GEN_PLD_RD_ERR | GEN_PLD_SEND_ERR | GEN_PLD_WR_ERR | GEN_CMD_WR_ERR | |||||
| Access | R | R | R | R | R | ||||
| Reset | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DPI_PLD_WR_ERR | EOTP_ERR | PKT_SIZE_ERR | CRC_ERR | ECC_MULTI_ERR | ECC_SINGLE_ERR | TO_LP_RX | TO_HS_TX | ||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 19 – DPI_BUFF_PLD_UNDER Input Video Interface Payload Buffer Underflow Status
Indicates that an underflow has occurred when reading the payload to build a DSI packet for Video mode.
Bit 12 – GEN_PLD_RECEV_ERR Generic Interface Payload Receive Error Status
Indicates that during a generic interface packet read back, the payload FIFO becomes full and the received data is corrupted.
Bit 11 – GEN_PLD_RD_ERR Generic Interface DCS Payload Read Error Status
Indicates that during a DCS read data, the payload FIFO becomes empty and the data sent to the interface is corrupted.
Bit 10 – GEN_PLD_SEND_ERR Generic Interface Payload Send Error Status
Indicates that during a generic interface packet build, the payload FIFO becomes empty and corrupt data is sent.
Bit 9 – GEN_PLD_WR_ERR Generic Interface Payload Write Error Status
Indicates that the system tried to write a payload data through the Generic interface and the FIFO is full. Therefore, the payload is not written.
Bit 8 – GEN_CMD_WR_ERR Generic Interface Command Write Error Status
Indicates that the system tried to write a command through the Generic interface and the FIFO is full. Therefore, the command is not written.
Bit 7 – DPI_PLD_WR_ERR Input Video Payload Write Error Status
Indicates that during a DPI pixel line storage, the payload FIFO becomes full and the data stored is corrupted.
Bit 6 – EOTP_ERR End Of Transmission Packet Error Status
Indicates that the EoTp packet has not been received at the end of the incoming peripheral transmission.
Bit 5 – PKT_SIZE_ERR Packet Size Error Status
Indicates that the packet size error has been detected during the packet reception.
Bit 4 – CRC_ERR CRC Error Status
Indicates that the CRC error has been detected in the received packet payload.
Bit 3 – ECC_MULTI_ERR ECC Multiple Error Status
Indicates that the ECC multiple error has been detected in a received packet.
Bit 2 – ECC_SINGLE_ERR ECC Single Error Status
Indicates that the ECC single error has been detected and corrected in a received packet.
Bit 1 – TO_LP_RX Low-Power Reception Timeout Status
Indicates that the low-power reception timeout counter reached the end and contention has been detected.
Bit 0 – TO_HS_TX High-Speed Transmission Timeout Status
Indicates that the high-speed transmission timeout counter reached the end and contention has been detected.