5.5.41 DSI D-PHY Control Register 1
| Name: | DSI_DPHY_TST_CTRL1 |
| Offset: | 0xB8 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| PHY_TESTEN | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| PHY_TESTDOUT[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PHY_TESTDIN[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 16 – PHY_TESTEN D-PHY Test Interface Operation Type
| Value | Name | Description |
|---|---|---|
| 0 | WRITEADDR | The data write operation is set on the rising edge of DSI_DPHY_TST_CTRL0.PHY_TESTCLK. |
| 1 | WRITEDATA | The address write operation is set on the falling edge of DSI_DPHY_TST_CTRL0.PHY_TESTCLK. |
Bits 15:8 – PHY_TESTDOUT[7:0] D-PHY Test Interface Data Out
PHY output 8-bit data bus for read-back and internal probing functionalities.
Bits 7:0 – PHY_TESTDIN[7:0] D-PHY Test Interface Data In
PHY test interface input 8-bit data bus for internal register programming and test functionalities access.