Introduction
Reference Document
1 Overview
2 CPU and Interconnect
3 Memories
4 System Controller
5 Image Subsystem
- 5.1 Overview
- 5.2 LCD Controller (LCDC)
- 5.3 Low Voltage Differential Signaling Controller (LVDSC)
- 5.4 2D Graphics Engine (GFX2D)
- 5.5 Display Serial Interface (DSI)
  - 5.5.1 Description
  - 5.5.2 Embedded Characteristics
  - 5.5.3 Block Diagram
  - 5.5.4 I/O Lines Description
  - 5.5.5 Product Dependencies
  - 5.5.6 Functional Description
  - 5.5 Register Summary
    - 5.5.1 DSI Power-Up Control Register
      DSI Power-Up Control Register
    - 5.5.2 DSI Clock Management Configuration Register
      DSI Clock Management Configuration Register
    - 5.5.3 DSI Input Video Virtual Channel ID Configuration Register
      DSI Input Video Virtual Channel ID Configuration Register
    - 5.5.4 DSI Input Video Color Coding Configuration Register
      DSI Input Video Color Coding Configuration Register
    - 5.5.5 DSI Input Video Polarity Configuration Register
      DSI Input Video Polarity Configuration Register
    - 5.5.6 DSI Input Video Timing for Low-Power Commands Configuration Register
      DSI Input Video Timing for Low-Power Commands Configuration Register
    - 5.5.7 DSI Protocol Configuration Register
      DSI Protocol Configuration Register
    - 5.5.8 DSI Read Generic Virtual Channel ID Configuration Register
      DSI Read Generic Virtual Channel ID Configuration Register
    - 5.5.9 DSI Mode of Operation Configuration Register
      DSI Mode of Operation Configuration Register
    - 5.5.10 DSI Video Mode Configuration Register
      DSI Video Mode Configuration Register
    - 5.5.11 DSI Video Mode Packet Size Configuration Register
      DSI Video Mode Packet Size Configuration Register
    - 5.5.12 DSI Video Mode Number of Chunks Configuration Register
      DSI Video Mode Number of Chunks Configuration Register
    - 5.5.13 DSI Video Mode Null Packets Size Configuration Register
      DSI Video Mode Null Packets Size Configuration Register
    - 5.5.14 DSI Video Mode HSA Time Configuration Register
      DSI Video Mode HSA Time Configuration Register
    - 5.5.15 DIS Video Mode HBP Time Configuration Register
      DIS Video Mode HBP Time Configuration Register
    - 5.5.16 DIS Video Mode HLINE Time Configuration Register
      DIS Video Mode HLINE Time Configuration Register
    - 5.5.17 DSI Video Mode VSA Lines Configuration Register
      DSI Video Mode VSA Lines Configuration Register
    - 5.5.18 DSI Video Mode VBP Lines Configuration Register
      DSI Video Mode VBP Lines Configuration Register
    - 5.5.19 DSI Video Mode VFP Lines Configuration Register
      DSI Video Mode VFP Lines Configuration Register
    - 5.5.20 DSI Video Mode VACTIVE Lines Configuration Register
      DSI Video Mode VACTIVE Lines Configuration Register
    - 5.5.21 DSI Command Mode Configuration Register
      DSI Command Mode Configuration Register
    - 5.5.22 DSI Generic Interface Header Register
      DSI Generic Interface Header Register
    - 5.5.23 DSI Generic Interface Payload Register
      DSI Generic Interface Payload Register
    - 5.5.24 DSI Command Packet Status Register
      DSI Command Packet Status Register
    - 5.5.25 DSI Timeout Counters Configuration Register
      DSI Timeout Counters Configuration Register
    - 5.5.26 DSI HS Read Response Timeout Counter Configuration Register
      DSI HS Read Response Timeout Counter Configuration Register
    - 5.5.27 DSI LP Read Response Timeout Counter Configuration Register
      DSI LP Read Response Timeout Counter Configuration Register
    - 5.5.28 DSI HS Write Response Timeout Counter Configuration Register
      DSI HS Write Response Timeout Counter Configuration Register
    - 5.5.29 DSI LP Write Response Timeout Counter Configuration Register
      DSI LP Write Response Timeout Counter Configuration Register
    - 5.5.30 DSI BTA Response Timeout Counter Configuration Register
      DSI BTA Response Timeout Counter Configuration Register
    - 5.5.31 DSI VSS Packet 3D Control Register
      DSI VSS Packet 3D Control Register
    - 5.5.32 DSI Clock Lane Control Register
      DSI Clock Lane Control Register
    - 5.5.33 DSI Clock Lane Switch Mode Timing Configuration Register
      DSI Clock Lane Switch Mode Timing Configuration Register
    - 5.5.34 DSI Data Lane Switch Mode Timing Configuration Register
      DSI Data Lane Switch Mode Timing Configuration Register
    - 5.5.35 DSI Reset and PLL Control Register
      DSI Reset and PLL Control Register
    - 5.5.36 DSI D-PHY Interface Configuration Register
      DSI D-PHY Interface Configuration Register
    - 5.5.37 DSI D-PHY ULPS Control Register
      DSI D-PHY ULPS Control Register
    - 5.5.38 DSI D-PHY Tx Trigger Control Register
      DSI D-PHY Tx Trigger Control Register
    - 5.5.39 DSI D-PHY Status Register
      DSI D-PHY Status Register
    - 5.5.40 DSI D-PHY Control Register 0
      DSI D-PHY Control Register 0
    - 5.5.41 DSI D-PHY Control Register 1
      DSI D-PHY Control Register 1
    - 5.5.42 DSI Interrupt Status Register 0
      DSI Interrupt Status Register 0
    - 5.5.43 DSI Interrupt Status Register 1
      DSI Interrupt Status Register 1
    - 5.5.44 DSI Interrupt Mask Configuration Register 0
      DSI Interrupt Mask Configuration Register 0
    - 5.5.45 DSI Interrupt Mask Configuration Register 1
      DSI Interrupt Mask Configuration Register 1
    - 5.5.46 DSI D-PHY Calibration Control Register
      DSI D-PHY Calibration Control Register
    - 5.5.47 DSI Interrupt Force Control Register 0
      DSI Interrupt Force Control Register 0
    - 5.5.48 DSI Interrupt Force Control Register 1
      DSI Interrupt Force Control Register 1
    - 5.5.49 DSI D-PHY Read Timing Configuration Register
      DSI D-PHY Read Timing Configuration Register
    - 5.5.50 DSI Video Mode Shadow Feature Control Register
      DSI Video Mode Shadow Feature Control Register
    - 5.5.51 DSI Input Video Virtual Channel ID Active Value Register
      DSI Input Video Virtual Channel ID Active Value Register
    - 5.5.52 DSI Input Video Color Coding Active Value Register
      DSI Input Video Color Coding Active Value Register
    - 5.5.53 DSI Input Video Timing for Low-Power Commands Active Value Register
      DSI Input Video Timing for Low-Power Commands Active Value Register
    - 5.5.54 DSI Video Mode Active Value Register
      DSI Video Mode Active Value Register
    - 5.5.55 DSI Video Mode Packet Size Active Value Register
      DSI Video Mode Packet Size Active Value Register
    - 5.5.56 DSI Video Mode Number of Chunks Active Value Register
      DSI Video Mode Number of Chunks Active Value Register
    - 5.5.57 DSI Video Mode Null Packets Size Active Value Register
      DSI Video Mode Null Packets Size Active Value Register
    - 5.5.58 DSI Video Mode HSA Time Active Value Register
      DSI Video Mode HSA Time Active Value Register
    - 5.5.59 DIS Video Mode HBP Time Active Value Register
      DIS Video Mode HBP Time Active Value Register
    - 5.5.60 DSI Video Mode HLINE Time Active Value Register
      DSI Video Mode HLINE Time Active Value Register
    - 5.5.61 DSI Video Mode VSA Lines Active Value Register
      DSI Video Mode VSA Lines Active Value Register
    - 5.5.62 DSI Video Mode VBP Lines Active Value Register
      DSI Video Mode VBP Lines Active Value Register
    - 5.5.63 DSI Video Mode VFP Lines Active Value Register
      DSI Video Mode VFP Lines Active Value Register
    - 5.5.64 DSI Video Mode VACTIVE Lines Active Value Register
      DSI Video Mode VACTIVE Lines Active Value Register
    - 5.5.65 DSI Video Mode Packet Status Register
      DSI Video Mode Packet Status Register
    - 5.5.66 DSI VSS Packet 3D Active Value Register
      DSI VSS Packet 3D Active Value Register
- 5.6 Camera Serial Interface (CSI)
- 5.7 CSI-2 Demultiplexer Controller (CSI2DC)
- 5.8 Image Sensor Controller (ISC)
6 Audio Subsystem
7 Security and Cryptography Subsystem
8 Connectivity Subsystem
9 USB Subsystem
10 Electrical and Mechanical Characteristics
11 Revision History
Microchip Information

5.5.39 DSI D-PHY Status Register

Name:	DSI_DPHY_STATUS
Offset:	0xB0
Reset:	–
Property:	Read-only


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8
				PHY_ULPSACTIVENOT3LANE	PHY_STOPSTATE3LANE	PHY_ULPSACTIVENOT2LANE	PHY_STOPSTATE2LANE	PHY_ULPSACTIVENOT1LANE
Access				R	R	R	R	R
Reset				–	–	–	–	–


Bit	7	6	5	4	3	2	1	0
	PHY_STOPSTATE1LANE	PHY_RXULPSESC0LANE	PHY_ULPSACTIVENOT0LANE	PHY_STOPSTATE0LANE	PHY_ULPSACTIVENOTCLK	PHY_STOPSTATECLKLANE	PHY_DIRECTION	PHY_LOCK
Access	R	R	R	R	R	R	R	R
Reset	–	–	–	–	–	–	–	–

Bit 12 – PHY_ULPSACTIVENOT3LANE D-PHY Ultra-Low-Power State Active on Data Lane 3 Status

Value	Description
0	Data lane 3 is in Ultra-Low-Power (ULP) state.
1	Data lane 3 is not in Ultra-Low-Power (ULP) state.

Bit 11 – PHY_STOPSTATE3LANE D-PHY Stop State on Data Lane 3 Status

Value	Description
0	Data lane 3 module is not in Stop state.
1	Data lane 3 module is in Stop state.

Bit 10 – PHY_ULPSACTIVENOT2LANE D-PHY Ultra-Low-Power State Active on Data Lane 2 Status

Value	Description
0	Data lane 2 is in Ultra-Low-Power (ULP) state.
1	Data lane 2 is not in Ultra-Low-Power (ULP) state.

Bit 9 – PHY_STOPSTATE2LANE D-PHY Stop State on Data Lane 2 Status

Value	Description
0	Data lane 2 module is not in Stop state.
1	Data lane 2 module is in Stop state.

Bit 8 – PHY_ULPSACTIVENOT1LANE D-PHY Ultra-Low-Power State Active on Data Lane 1 Status

Value	Description
0	Data lane 1 is in Ultra-Low-Power (ULP) state.
1	Data lane 1 is not in Ultra-Low-Power (ULP) state.

Bit 7 – PHY_STOPSTATE1LANE D-PHY Stop State on Data Lane 1 Statu

Value	Description
0	Data lane 1 module is not in Stop state.
1	Data lane 1 module is in Stop state.

Bit 6 – PHY_RXULPSESC0LANE Ultra-Low-Power State Escape Code Reception

Value	Description
0	Data lane 0 is not in Ultra Low-Power state after reception of the Ultra Low-Power state Escape code.
1	Data lane 0 is in Ultra Low-Power state after reception of the Ultra Low-Power state Escape code.

Bit 5 – PHY_ULPSACTIVENOT0LANE D-PHY Ultra-Low-Power State Active on Data Lane 0 Status

Value	Description
0	Data lane 0 is in Ultra-Low-Power (ULP) state.
1	Data lane 0 is not in Ultra-Low-Power (ULP) state.

Bit 4 – PHY_STOPSTATE0LANE D-PHY Stop State on Data Lane 0 Status

Value	Description
0	Data lane 0 module is not in Stop state.
1	Data lane 0 module is in Stop state.

Bit 3 – PHY_ULPSACTIVENOTCLK D-PHY Ultra-Low-Power State Active on Clock Lane Status

Value	Description
0	The clock lane is in Ultra-Low-Power (ULP) state.
1	The clock lane is not in the Ultra-Low-Power state.

Bit 2 – PHY_STOPSTATECLKLANE D-PHY Stop State Clock Lane Status

Value	Description
0	The clock lane module is not in Stop state.
1	The clock lane module is in Stop state.

Bit 1 – PHY_DIRECTION D-PHY Direction Status

Used to indicate the current direction of the lane interconnect.

Value	Description
0	The lane interconnect is in Transmit mode.
1	The lane interconnect is in Receive mode.

Bit 0 – PHY_LOCK D-PHY Lock Status

When set, indicates that the PLL acquired the lock with the reference clock.

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