5.5.24 DSI Command Packet Status Register

Name: DSI_CMD_PKT_STATUS
Offset: 0x74
Reset: 0x00050015
Property: Read-only

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
     GEN_BUFF_PLD_FULLGEN_BUFF_PLD_EMPTYGEN_BUFF_CMD_FULLGEN_BUFF_CMD_EMPTY 
Access RRRR 
Reset 0101 
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
  GEN_RD_CMD_BUSYGEN_PLD_R_FULLGEN_PLD_R_EMPTYGEN_PLD_W_FULLGEN_PLD_W_EMPTYGEN_CMD_FULLGEN_CMD_EMPTY 
Access RRRRRRR 
Reset 0010101 

Bit 19 – GEN_BUFF_PLD_FULL Generic Payload Internal Buffer Full

Indicates the full status of the generic payload internal buffer.

Bit 18 – GEN_BUFF_PLD_EMPTY Generic Payload Internal Buffer Empty

Indicates the empty status of the generic payload internal buffer.

Bit 17 – GEN_BUFF_CMD_FULL Generic Command Internal Buffer Full

Indicates the full status of the generic command internal buffer.

Bit 16 – GEN_BUFF_CMD_EMPTY Generic Command Internal Buffer Empty

Indicates the empty status of the generic command internal buffer.

Bit 6 – GEN_RD_CMD_BUSY Generic Interface Read Command FIFO Busy

Set when a read command is issued and cleared when the entire response is stored in the FIFO for the generic interface.

Bit 5 – GEN_PLD_R_FULL Generic Interface Read Payload FIFO Full

This bit indicates the full status of the generic read payload FIFO.

Bit 4 – GEN_PLD_R_EMPTY Generic Interface Read Payload FIFO Empty

Indicates the empty status of the generic read payload FIFO.

Bit 3 – GEN_PLD_W_FULL Generic Interface Write Payload FIFO Full

Indicates the full status of the generic write payload FIFO.

Bit 2 – GEN_PLD_W_EMPTY Generic Interface Write Payload FIFO Empty

Indicates the empty status of the generic write payload FIFO.

Bit 1 – GEN_CMD_FULL Generic Interface Command FIFO Full

Indicates the full status of the generic command FIFO.

Bit 0 – GEN_CMD_EMPTY Generic Interface Command FIFO Empty

Indicates the empty status of the generic command FIFO.