10.1.30.3 Register File Implementation Rules/Timing Diagrams

The following table lists the timing waveform terminology used in the implementation rules and timing diagrams for the Register File.

Table 10-120. Timing Waveform Terminology
TermDescriptionTermDescription
tckhlClock high/low periodtdsuData setup time
trpReset pulse widthtrcoData valid after clock high/low
twesuWrite enable setup timetraoData valid after read address has changed
tresuRead enable setup timetcoFlip-flop clock to output
Figure 10-36. Ram Write Cycle
þÿ
Figure 10-37. RAM Synchronous Read Cycle
þÿ
Figure 10-38. RAM Asynchronous Read Cycle
þÿ