10.1.12.1.1 Axcelerator DDR Register

The following image describes an axcelerator DDR register.

Figure 10-13. Axcelerator DDR Register
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The following table describes the ports of an Input Buffer plus DDR Register for Axcelerator.

Table 10-49. Port Description - Input Buffer plus DDR Register for Axcelerator
Port Name Size Type Required/Optional Function
PAD WIDTH Input Required Input Data
QR WIDTH Output Required Output Data
QF WIDTH Output RequiredOutput Data
E 1 Input Required Enable
CLK 1 Input Required Clock
CLR 1 Input Required Clear
PRE 1 Input Required Preset