10.1.33.2 Shift Register I/O Description
The following table lists the I/O description of a Shift Register .
| Name | Type | Required/Optional | Description |
|---|---|---|---|
| Data | IN | Optional | Register load input data |
| Shiftin | IN | Optional | Shift in signal |
| Aclr | IN | Optional | Asynchronous register reset |
| Enable | IN | Optional | Synchronous parallel load enable |
| Shiften | IN | Required | Synchronous register shift enable |
| Clock | IN | Required | Clock |
| Q | OUT | Optional | Register output bus |
| Shiftout | OUT | Optional | Serial output |