10.1.33.1 Shift Register Functionality

Shift registers have parallel-in/parallel-out (PIPO), parallel-in/serial-out (PISO), serial-in/parallel-out (SIPO) and serial-in/serial-out (SISO) architecture. The registers are WIDTH bits. They are clocked on the rising (RISE) or falling (FALL) edge of the clock signal (CLK_EDGE).

The Clear signal (CLR_POLARITY), active high or low, provides an asynchronous reset of the registers to “000…0”. You may choose to not implement the reset function.

Shift registers can be loaded with Data. The Enable signal (EN_POLARITY), active high or low, provides a synchronous load enable operation with respect to the clock signal Clock. You may choose to not implement this function. Shift registers are then implemented in a serial-in mode (SIPO or SISO).

Shift registers have a shift enable signal Shiften (SHEN_POLARITY) that can be active high or low. When Shiften is active, the register is shifted internally. The LSB is loaded with Shiftin.

In the current implementation, Enable has priority over Shiften.

Table 10-131. Functional Description^A
Data	Aclr	Enable	Shiften	Clock	QB	ShiftoutC
X	0	X	X	X	0	0
X	1	X	X	¬	Qn	Qn = [WIDTH-1]
X	1	0	0	ƒ	Qn	Qn = [WIDTH-1]
X	1	0	1	ƒ	Qn[ WIDTH-2:0] &&Shif-tin	Qn = [WIDTH-1]
m	1	1	X	ƒ	Qn+1 = m	Qn+1 =m [WIDTH-1]

Note:

Aclr is active low, Enable is active high, Shiften is active high, Clock is rising.
For the PISO and SISO implementations, Q is an internal register.
For the PIPO and SIPO implementations, Shiftout is not present.