10.1.34.1 Storage Register Functionality

Storage registers have a parallel-in/parallel-out (PIPO) architecture. The registers are WIDTH bits. They are clocked on the rising (RISE) or falling (FALL) edge of the clock Clock (CLK_EDGE).

The Clear signal (CLR_POLARITY), active high or low, provides an asynchronous reset of the registers to “000…0”. You may choose to not implement the reset function.

The Enable signal (EN_POLARITY), active high or low, provides a synchronous load enable operation with respect to the Clock signal. You can choose to not implement this function. Storage registers are then loaded with a new value every clock cycle.

The Set signal, active high or low, provides an asynchronous set of the registers to "1111...1". You may choose not to implement the Set function.