11.2.45 CAN FIFO Control Register x Low (x = 1 to 8)
- This bit can only be modified in
Configuration mode (OPMOD[2:0] =
100).
Legend: S = Settable bit; HC = Hardware Clearable bit
| Name: | C1FIFOCONxL |
| Offset: | 0x61C, 0x628, 0x634, 0x640, 0x64C, 0x658, 0x664, 0x670 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| FRESET | TXREQ | UINC | |||||||
| Access | S/HC | R/W/HC | S/HC | ||||||
| Reset | 1 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TXEN | RTREN | RXTSEN | TXATIE | RXOVIE | TFERFFIE | TFHRFHIE | TFNRFNIE | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 10 – FRESET FIFO Reset bit
| Value | Description |
|---|---|
1 |
FIFO will be reset when the bit is set and cleared by hardware when the FIFO is reset; the user should poll whether this bit is clear before taking any action. |
0 |
No effect. |
Bit 9 – TXREQ Message Send Request bit
TXEN = 0 (FIFO configured as a receive FIFO):
This bit has no effect.
TXEN = 1 (FIFO configured as a transmit
FIFO):
| Value | Description |
|---|---|
1 |
Requests sending a message; the bit will automatically clear when all the messages queued in the FIFO are successfully sent. |
0 |
Clearing the bit to ‘ |
Bit 8 – UINC Increment Head/Tail bit
TXEN = 1 (FIFO configured as a transmit
FIFO):
When this bit is set, the FIFO head will increment by a single message.
TXEN = 0 (FIFO configured as a receive
FIFO):
When this bit is set, the FIFO tail will increment by a single message.
Bit 7 – TXEN TX/RX Buffer Selection bit
| Value | Description |
|---|---|
1 |
Transmits message object. |
0 |
Receives message object. |
Bit 6 – RTREN Auto-Remote Transmit (RTR) Enable bit
| Value | Description |
|---|---|
1 |
When a Remote Transmit is received, TXREQ will be set. |
0 |
When a Remote Transmit is received, TXREQ will be unaffected. |
Bit 5 – RXTSEN Received Message Timestamp Enable bit(1)
| Value | Description |
|---|---|
1 |
Captures the timestamp in the received message object in RAM. |
0 |
Does not capture the timestamp. |
Bit 4 – TXATIE Transmit Attempts Exhausted Interrupt Enable bit
| Value | Description |
|---|---|
1 |
Enables interrupt. |
0 |
Disables interrupt. |
Bit 3 – RXOVIE Overflow Interrupt Enable bit
| Value | Description |
|---|---|
1 |
Interrupt is enabled for overflow event. |
0 |
Interrupt is disabled for overflow event. |
Bit 2 – TFERFFIE Transmit/Receive FIFO Empty/Full Interrupt Enable bit
TXEN = 1 (FIFO configured as a transmit
FIFO):
Transmit FIFO Empty Interrupt Enable.
| Value | Description |
|---|---|
1 | Interrupt is enabled for FIFO empty. |
0 | Interrupt is disabled for FIFO empty. |
TXEN = 0 (FIFO configured as a receive FIFO):
Receive FIFO Full Interrupt Enable.
| Value | Description |
|---|---|
1 | Interrupt is enabled for FIFO full. |
0 | Interrupt is disabled for FIFO full. |
Bit 1 – TFHRFHIE Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable bit
TXEN = 1 (FIFO configured as a transmit
FIFO):
Transmit FIFO Half Empty Interrupt Enable.
| Value | Description |
|---|---|
1 | Interrupt is enabled for FIFO half empty. |
0 | Interrupt is disabled for FIFO half empty. |
TXEN = 0 (FIFO configured as a receive FIFO):
Receive FIFO Half Full Interrupt Enable.
| Value | Description |
|---|---|
1 | Interrupt is enabled for FIFO half full. |
0 | Interrupt is disabled for FIFO half full. |
Bit 0 – TFNRFNIE Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable bit
TXEN = 1 (FIFO configured as a transmit
FIFO):
Transmit FIFO Not Full Interrupt Enable.
| Value | Description |
|---|---|
1 | Interrupt is enabled for FIFO not full. |
0 | Interrupt is disabled for FIFO not full. |
TXEN = 0 (FIFO configured as a receive FIFO):
Receive FIFO Not Empty Interrupt Enable.
| Value | Description |
|---|---|
1 | Interrupt is enabled for FIFO not empty. |
0 | Interrupt is disabled for FIFO not empty. |