11.2.8 CAN Transmitter Delay Compensation Register High

Note:
  1. This register can only be modified in Configuration mode (OPMOD[2:0] = 100).
Name: C1TDCH(1)
Offset: 0x5CE

Bit 15141312111098 
       EDGFLTENSID11EN 
Access R/WR/W 
Reset 00 
Bit 76543210 
       TDCMOD[1:0] 
Access R/WR/W 
Reset 10 

Bit 9 – EDGFLTEN Enable Edge Filtering During Bus Integration State bit

ValueDescription
1

Edge filtering is enabled according to ISO 11898-1:2015.
0

Edge filtering is disabled.

Bit 8 – SID11EN Enable 12-Bit SID in CAN FD Base Format Messages bit

ValueDescription
1

RRS is used as SID11 in CAN FD base format messages: SID[11:0] = {SID[10:0], SID11}.
0

Does not use RRS; SID[10:0].

Bits 1:0 – TDCMOD[1:0] Transmitter Delay Compensation Mode bits (Secondary Sample Point (SSP))

ValueDescription
10-11

Auto: Measures delay and adds TDCO[6:0]
01

Manual: Does not measure, uses TDCV[5:0] + TDCO[6:0] from register
00

Disabled