11.2.23 CAN Transmit Attempt Interrupt Status Register Low
Note:
- C1TXATIFL: FIFO: TFATIFx (flag needs to be cleared in the FIFO register).
- TFATIF0 is for the Transmit Queue.
| Name: | C1TXATIFL(1) |
| Offset: | 0x5EC |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| TFATIF[15:8] | |||||||||
| Access | U | U | U | U | U | U | U | U | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TFATIF[7:0] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 15:8 – TFATIF[15:8] Unimplemented
Bits 7:0 – TFATIF[7:0] Transmit FIFO/TXQ Attempt Interrupt Pending bits(2)
| Value | Description |
|---|---|
1 |
Interrupt is pending. |
0 |
Interrupt is not pending. |