11.2.33 CAN Transmit Event FIFO Control Register Low

Legend: S = Settable bit; HC = Hardware Clearable bit

Name: C1TEFCONL
Offset: 0x600

Bit 15141312111098 
      FRESET UINC 
Access S/HCS/HC 
Reset 10 
Bit 76543210 
   TEFTSEN TEFOVIETEFFIETEFHIETEFNEIE 
Access R/WR/WR/WR/WR/W 
Reset 00000 

Bit 10 – FRESET FIFO Reset bit

ValueDescription
1 FIFO will be reset when the bit is set and cleared by hardware when the FIFO is reset; the user should poll whether this bit is clear before taking any action.
0 No effect.

Bit 8 – UINC Increment Tail bit

ValueDescription
1 When this bit is set, the FIFO tail will increment by a single message.
0 FIFO tail will not increment.

Bit 5 – TEFTSEN Transmit Event FIFO Timestamp Enable bit

ValueDescription
1 Timestamp elements in TEF.
0 Does not timestamp elements in TEF.

Bit 3 – TEFOVIE Transmit Event FIFO Overflow Interrupt Enable bit

ValueDescription
1 Interrupt is enabled for overflow event.
0 Interrupt is disabled for overflow event.

Bit 2 – TEFFIE Transmit Event FIFO Full Interrupt Enable bit

ValueDescription
1 Interrupt is enabled for FIFO full.
0 Interrupt is disabled for FIFO full.

Bit 1 – TEFHIE Transmit Event FIFO Half Full Interrupt Enable bit

ValueDescription
1 Interrupt is enabled for FIFO half full.
0 Interrupt is disabled for FIFO half full.

Bit 0 – TEFNEIE Transmit Event FIFO Not Empty Interrupt Enable bit

ValueDescription
1 Interrupt is enabled for FIFO not empty.
0 Interrupt is disabled for FIFO not empty.