11.2.20 CAN Transmit Interrupt Status Register High
Note:
- C1TXIFH: FIFO: TFIFx = ‘or’ of the enabled TX FIFO flags (flags need to be cleared in the FIFO register).
| Name: | C1TXIFH(1) |
| Offset: | 0x5E6 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| TFIF[31:24] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TFIF[23:16] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 15:0 – TFIF[31:16] Transmit FIFO/TXQ Attempt Interrupt Pending bits
| Value | Description |
|---|---|
1 |
One or more enabled transmit FIFO/TXQ interrupts are pending. |
0 |
No enabled transmit FIFO/TXQ interrupts are pending. |