11.2.35 CAN Transmit Event FIFO Status Register

Note:
  1. These bits are read-only and reflect the status of the FIFO.

Legend: HC = Hardware Clearable bit; S = Settable bit can Set by ‘1’

Name: C1TEFSTA
Offset: 0x604

Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
     TEFOVIFTEFFIFTEFHIFTEFNEIF 
Access S/HCRRR 
Reset 0000 

Bit 3 – TEFOVIF Transmit Event FIFO Overflow Interrupt Flag bit

ValueDescription
1 Overflow event has occurred.
0 No overflow event has occurred.

Bit 2 – TEFFIF  Transmit Event FIFO Full Interrupt Flag bit(1)

ValueDescription
1

FIFO is full.
0

FIFO is not full.

Bit 1 – TEFHIF  Transmit Event FIFO Half Full Interrupt Flag bit(1)

ValueDescription
1

FIFO is ≥ half full.
0

FIFO is < half full.

Bit 0 – TEFNEIF  Transmit Event FIFO Not Empty Interrupt Flag bit(1)

ValueDescription
1

FIFO is not empty.
0

FIFO is empty.