11.2.54 CAN Mask Register x Low (x = 0 to 15)
| Name: | C1MASKxL |
| Offset: | 0x690, 0x698, 0x6A0, 0x6A8, 0x6B0, 0x6B8, 0x6C0, 0x6C8, 0x6D0, 0x6D8, 0x6E0, 0x6E8, 0x6F0, 0x6F8, 0x700, 0x708 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| MEID[4:0] | MSID[10:8] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| MSID[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 15:11 – MEID[4:0] Extended Identifier Mask bits
In DeviceNet™ mode, these are the mask bits for the first two data bytes.