8.2.2.14 Output Enable for PORTB Register
| Name: | TRISB |
| Offset: | 0xE1E |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| TRISB[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TRISB[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | |
Bits 15:0 – TRISB[15:0] Output Enable for PORTB bits
| Value | Description |
|---|---|
1 |
LATx[n] is not driven on the PORTx[n] pin. |
0 |
LATx[n] is driven on the PORTx[n] pin. |