10.1.35.1 Storage Latch Functionality
Latches have a parallel-in/parallel-out architecture (PIPO). The latches are WIDTH bits. The latches are gated on the active high (HIGH) or low (LOW) state of the gate Gate (GATE_POLARITY).
The Clear signal (CLR_POLARITY), when active high or low, provides an asynchronous reset of the latch to “000…0”. You may choose to not implement this function.
The Enable signal (EN_POLARITY), when active high or low, provides a synchronous latch enable operation with respect to the gate Gate. You may choose to not implement this function. Latches are then loaded with a new value when both Enable and Gate are active.
| Data | Aclr | Enable | Gate | Q |
|---|---|---|---|---|
| X | 0 | X | X | 0's |
| X | 1 | X | 0 | Qn |
| X | 1 | 0 | 1 | Qn |
| m | 1 | 1 | 1 | Qn+1 = m |
Note: Aclr is active low, Enable is active high, Shiften is active
high, Clock is rising.