10.1.28.1 Multiplier Functionality

The following table lists the functionality description of a Multiplier.

Table 10-104. Functional Description
DataA	DataB	Mult1A
m	n	m * n

Note: If pipelined, the sum is correct (available) after <latency> cycles. Latency is a function of WIDTHA and WIDTHB, or the number of pipelined stages mentioned specifically (For example 1 or 2 pipelines).

Table 10-105. Functional Description
DataA	DataB	Mult0/1A
m	n	Mult1 + Mult2 = m * n

Note: Mult1<0> is always 0.

In the Architecture Comparison following tables, WIDTHA = WIDTHB.

Table 10-106. Axcelerator Multiplier Architecture Comparison: Speed
Architecture/Speed	1 (fastest)	2	3 (slowest)
Parallel-2 Array Multiplier	width <= 8 bit	8 bit < width <= 10 bit	width > 10 bit
FC Booth-1	8 bit < width <= 20 bit	width <= 8 bit or width > 20 bit	—
FC Booth-2	width > 20 bit	10 bit < width <= 20 bit	width <= 10 bit

Table 10-107. Axcelerator Multiplier Architecture Comparison: Area
Architecture/Speed	1 (smallest)	2	3 (largest)
Parallel-2 Array Multiplier	always	—	—
FC Booth-1	—	—	always
FC Booth-2	—	always	—