8.7.72 Core Control Register
Note:
- The IPL3 bit is concatenated with the IPL[2:0] bits (SR[7:5]) to form the CPU Interrupt Priority Level.
Legend: C = Clearable bit
| Name: | CORCON |
| Offset: | 0x44 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| VAR | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| IPL3 | |||||||||
| Access | R/C | ||||||||
| Reset | 0 |
Bit 15 – VAR Variable Exception Processing Latency Control bit
| Value | Description |
|---|---|
1 |
Variable exception processing is enabled |
0 |
Fixed exception processing is enabled |
Bit 3 – IPL3 CPU Interrupt Priority Level Status bit 3(1)
| Value | Description |
|---|---|
1 |
CPU Interrupt Priority Level is greater than 7 |
0 |
CPU Interrupt Priority Level is 7 or less |