8.7.59 Interrupt Priority Register 32
| Name: | IPC32 |
| Offset: | 0x880 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SPI3IP[2:0] | |||||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 1 | 0 | 0 | ||||||
Bits 2:0 – SPI3IP[2:0] SPI3 Error Interrupt Priority bits
| Value | Description |
|---|---|
| 7 | Interrupt Priority Level 7 (highest) |
| 6 | Interrupt Priority Level 6 |
| 5 | Interrupt Priority Level 5 |
| 4 | Interrupt Priority Level 4 (default) |
| 3 | Interrupt Priority Level 3 |
| 2 | Interrupt Priority Level 2 |
| 1 | Interrupt Priority Level 1 |
| 0 | Interrupt Priority Level 0 (lowest) |