8.7.71 CPU STATUS Register
Note:
- The IPL[2:0] bits are concatenated
with the IPL[3] bit (CORCON[3]) to form the CPU Interrupt Priority Level. The
value in parentheses indicates the IPL, if IPL[3] =
1. User interrupts are disabled when IPL[3] =1. - The IPL[2:0] Status bits are
read-only when the NSTDIS bit (INTCON1[15]) =
1.
Legend: C = Clearable bit
| Name: | SR |
| Offset: | 0x42 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| IPL[2:0] | |||||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 | ||||||
Bits 7:5 – IPL[2:0] CPU Interrupt Priority Level Status bits(1,2)
| Value | Description |
|---|---|
111 |
CPU Interrupt Priority Level is 7 (15); user interrupts are disabled |
110 |
CPU Interrupt Priority Level is 6 (14) |
101 |
CPU Interrupt Priority Level is 5 (13) |
100 |
CPU Interrupt Priority Level is 4 (12) |
011 |
CPU Interrupt Priority Level is 3 (11) |
010 |
CPU Interrupt Priority Level is 2 (10) |
001 |
CPU Interrupt Priority Level is 1 (9) |
000 |
CPU Interrupt Priority Level is 0 (8) |