8.7.77 Interrupt Control and Status Register
| Name: | INTTREG |
| Offset: | 0x8C8 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| VHOLD | ILR[3:0] | ||||||||
| Access | R | R | R | R | R | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| VECNUM[7:0] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 13 – VHOLD Vector Number Capture Enable bit
| Value | Description |
|---|---|
1 |
VECNUM[7:0] bits read current value of vector number encoding tree (i.e., highest priority pending interrupt) |
0 |
Vector number latched into VECNUM[7:0] at Interrupt Acknowledge and retained until next IACK |
Bits 11:8 – ILR[3:0] New CPU Interrupt Priority Level bits
| Value | Description |
|---|---|
1111 |
CPU Interrupt Priority Level is 15 |
| . . . | |
0001 |
CPU Interrupt Priority Level is 1 |
0000 |
CPU Interrupt Priority Level is 0 |
Bits 7:0 – VECNUM[7:0] Vector Number of Pending Interrupt bits
| Value | Description |
|---|---|
11111111 |
255, Reserved; do not use |
| . . . | |
00001001 |
9, IC1 – Input Capture 1 |
00001000 |
8, INT0 – External Interrupt 0 |
00000111 |
7, Reserved; do not use |
00000110 |
6, Generic soft error trap |
00000101 |
5, Reserved; do not use |
00000100 |
4, Math error trap |
00000011 |
3, Stack error trap |
00000010 |
2, Generic hard trap |
00000001 |
1, Address error trap |
00000000 |
0, Oscillator fail trap |