8.7.65 Interrupt Priority Register 43

Name: IPC43
Offset: 0x896

Bit 15141312111098 
  CLC3PEIP[2:0] PEVTFIP[2:0] 
Access R/WR/WR/WR/WR/WR/W 
Reset 100100 
Bit 76543210 
  PEVTEIP[2:0] PEVTDIP[2:0] 
Access R/WR/WR/WR/WR/WR/W 
Reset 100100 

Bits 14:12 – CLC3PEIP[2:0] CLC3 Positive Edge Interrupt Priority bits

ValueDescription
7 Interrupt Priority Level 7 (highest)
6 Interrupt Priority Level 6
5 Interrupt Priority Level 5
4 Interrupt Priority Level 4 (default)
3 Interrupt Priority Level 3
2 Interrupt Priority Level 2
1 Interrupt Priority Level 1
0 Interrupt Priority Level 0 (lowest)

Bits 10:8 – PEVTFIP[2:0] PWM Event F Interrupt Priority bits

ValueDescription
7 Interrupt Priority Level 7 (highest)
6 Interrupt Priority Level 6
5 Interrupt Priority Level 5
4 Interrupt Priority Level 4 (default)
3 Interrupt Priority Level 3
2 Interrupt Priority Level 2
1 Interrupt Priority Level 1
0 Interrupt Priority Level 0 (lowest)

Bits 6:4 – PEVTEIP[2:0] PWM Event E Interrupt Priority bits

ValueDescription
7 Interrupt Priority Level 7 (highest)
6 Interrupt Priority Level 6
5 Interrupt Priority Level 5
4 Interrupt Priority Level 4 (default)
3 Interrupt Priority Level 3
2 Interrupt Priority Level 2
1 Interrupt Priority Level 1
0 Interrupt Priority Level 0 (lowest)

Bits 2:0 – PEVTDIP[2:0] PWM Event D Interrupt Priority bits

ValueDescription
7 Interrupt Priority Level 7 (highest)
6 Interrupt Priority Level 6
5 Interrupt Priority Level 5
4 Interrupt Priority Level 4 (default)
3 Interrupt Priority Level 3
2 Interrupt Priority Level 2
1 Interrupt Priority Level 1
0 Interrupt Priority Level 0 (lowest)