43.8.43 Switch off timer value.

Table 43-44. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	RNG_Control_Registers__SwOffTmrVal
Offset:	0x11040
Reset:	0x0000FFFF
Property:	RW

Bits 15:0 – SwOffTmrVal[15:0] Number of clk cycles to wait before stopping the rings after the FIFO is full.