43.8.48 AIS31 status register.

Table 43-49. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	RNG_Control_Registers__AIS31Status
Offset:	0x11054
Reset:	0x00000000
Property:	RW


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16
							PrelimNoiseAlarmRep	PrelimNoiseAlarmRng
Access							RW	RW
Reset							0	0


Bit	15	14	13	12	11	10	9	8
	NumPrelimAlarms[15:8]
Access	RW	RW	RW	RW	RW	RW	RW	RW
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	NumPrelimAlarms[7:0]
Access	RW	RW	RW	RW	RW	RW	RW	RW
Reset	0	0	0	0	0	0	0	0

Bit 17 – PrelimNoiseAlarmRep Last preliminary noise alarm occurred due to consecutive high X**2.

Bit 16 – PrelimNoiseAlarmRng Last preliminary noise alarm occurred due to history value out of range.

Bits 15:0 – NumPrelimAlarms[15:0] Number of preliminary noise alarms since counter was last cleared.

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