43.8.1 Control Register A
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | CTRLA |
| Offset: | 0x0 |
| Reset: | 0x00000000 |
| Property: | R/W |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RUNSTDBY | PRIV | ENABLE | SWRST | ||||||
| Access | R/W | R/W | R/W | R/S/HC | |||||
| Reset | 0 | 0 | 0 | 0 |
Bit 6 – RUNSTDBY Run In Standby bit
| Value | Name | Description |
|---|---|---|
| 1 | If enabled, the CAM clock remains requested in Standby Sleep mode. | |
| 0 | CAM clock is disabled in Standby Sleep mode, clock requests are de-asserted after any pending bus transactions or requests are completed. |
Bit 2 – PRIV Privileged Access Only - This bit affects all Wrapper and EIP registers.
This bit affects all Wrapper and EIP registers.
| Value | Name | Description |
|---|---|---|
| 1 | CAM registers only accessible in privileged mode. Master Requests are also privileged. | |
| 0 | CAM registers accessible in privileged and unprivileged modes. Master Requests are NOT privileged |
Bit 1 – ENABLE Setting this bit also sets the SYNCBUSY.ENABLE to 1. SYNCBUSY.ENABLE stays 1 until Enable / Disable sequence completes.
Setting this bit also sets the SYNCBUSY.ENABLE to 1. SYNCBUSY.ENABLE stays 1 until Enable or Disable sequence completes.
| Value | Name | Description |
|---|---|---|
| 1 | CAM clock is requested and macro is enabled. | |
| 0 | CAM clock is not requested and macros is disabled. |
Bit 0 – SWRST Write '1' to reset registers and internal state. Writing '0' has no effect. SWRST stays high until reset completes. Setting this bit also sets the SYNCBUSY.SWRST to 1. SYNCBUSY.SWRST stays 1 until reset sequence completes.
Write ‘1’ to reset registers and internal state. Writing ‘0’ has no effect. SWRST stays high until reset completes. Setting this bit also sets the SYNCBUSY.SWRST to 1. SYNCBUSY.SWRST stays 1 until reset sequence completes.
| Value | Description |
|---|---|
| 0x0 | No effect |
| 0x1 | Reset registers and internal state |