43.8.54 Timer register.

Table 43-55. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	PK_Registers__Timer
Offset:	0x12014
Reset:	0x00000000
Property:	RW


Bit	31	30	29	28	27	26	25	24
	Timer[30:23]
Access	RW	RW	RW	RW	RW	RW	RW	RW
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	Timer[22:15]
Access	RW	RW	RW	RW	RW	RW	RW	RW
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	Timer[14:7]
Access	RW	RW	RW	RW	RW	RW	RW	RW
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	Timer[6:0]
Access	RW	RW	RW	RW	RW	RW	RW
Reset	0	0	0	0	0	0	0

Bits 31:1 – Timer[30:0] Number of core clock cycles.

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