43.8.30 FIFO threshold register.

Table 43-31. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	RNG_Control_Registers__FIFOThreshold
Offset:	0x11008
Reset:	0x00000001
Property:	RW

Bits 1:0 – FIFOThreshold[1:0] FIFO level below which the module leaves the idle state to refill the FIFO, expressed in number of 128bit blocks.