43.8.22
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | CryptoMaster_HWConf_Registers__BA411E_AES_HW_CFG_1 |
| Offset: | 0x10404 |
| Reset: | 0x1F0301FF |
| Property: | R |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| BA411E_AES_HW_CFG_GLITCHPROTECTION | BA411E_AES_HW_CFG_CXSWITCH | BA411E_AES_HW_CFG_KEYSIZE[2:0] | |||||||
| Access | R | R | R | R | R | ||||
| Reset | 1 | 1 | 1 | 1 | 1 | ||||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| BA411E_AES_HW_CFG_MASKING | BA411E_AES_HW_CFG_CS | ||||||||
| Access | R | R | |||||||
| Reset | 1 | 1 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| BA411E_AES_HW_CFG_MODE[8] | |||||||||
| Access | R | ||||||||
| Reset | 1 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| BA411E_AES_HW_CFG_MODE[7:0] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |