43.8.39 Status register.

Table 43-40. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	RNG_Control_Registers__Status
Offset:	0x11030
Reset:	0x00000000
Property:	RW


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8
					FifoAccFail	StartUpFail	AlmInt	PreInt
Access					RW	R	RW	RW
Reset					0	0	0	0


Bit	7	6	5	4	3	2	1	0
	FullInt		PropFail	RepFail	State[2:0]			TestDataBusy
Access	RW		RW	RW	R	R	R	R
Reset	0		0	0	0	0	0	0

Bit 11 – FifoAccFail Set when a FIFO data read is performed while the NDRNG is disabled AND has its FIFO empty (FIFOLevel = 0).

Bit 10 – StartUpFail Start-up test failure.

Bit 9 – AlmInt AIS31 noise alarm interrupt status.

Bit 8 – PreInt AIS31 preliminary noise alarm interrupt status.

Bit 7 – FullInt FIFO full status.

Bit 5 – PropFail NIST-800-90B adaptive Proportion Test (1024-sample window) interrupt status.

Bit 4 – RepFail NIST-800-90B repetition Count Test interrupt status.

Bits 3:1 – State[2:0] State of the control FSM: 000: Reset, 001: Startup, 010: Idle (Rings On), 011: Idle (Rings Off), 100: Fill FIFO, 101: Error, 110: Unused, 111: Unused.

Bit 0 – TestDataBusy High when data written to TestData register is being processed. (see section 4.7)

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