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43.8.55 Hardware configuration register.
Table 43-56. Register Bit Attribute
Legend Symbol Description Symbol Description Symbol Description R Readable bit HC Cleared by Hardware (Grey cell) Unimplemented W Writable bit HS Set by Hardware X Bit is unknown at Reset K Write to clear S Software settable bit — —
Name: PK_Registers__HwConfig Offset: 0x12018 Reset: 0x43F30200 Property: R
Bit 31 30 29 28 27 26 25 24 DisableCM DisableClrMem DisableSMx AHBMaster X25519 Access R R R R R Reset 0 1 0 1 1
Bit 23 22 21 20 19 18 17 16 P192 P521 P384 P256 ECC BinaryField PrimeField Access R R R R R R R Reset 1 1 1 1 0 1 1
Bit 15 14 13 12 11 10 9 8 NbMult[3:0] MaxOpSize[11:8] Access R R R R R R R R Reset 0 0 0 0 0 0 1 0
Bit 7 6 5 4 3 2 1 0 MaxOpSize[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0
Bit 31 – DisableCM State of DisableCM input (high when counter-measures are disabled).
Bit 30 – DisableClrMem State of DisableClrMem input (high when automatic clear of the RAM after reset is disabled).
Bit 29 – DisableSMx State of DisableSMx input (high when SM2/SM9 operations are disabled).
Bit 25 – AHBMaster '0': Memory access through AHB Slave and internally in the PKE. '1': Memory access through AHB Master, outside the PKE.
Bit 24 – X25519 Support Curve25519/Ed25519 acceleration.
Bit 23 – P192 Support ECC P192 acceleration.
Bit 22 – P521 Support ECC P521 acceleration.
Bit 21 – P384 Support ECC P384 acceleration.
Bit 20 – P256 Support ECC P256 acceleration.
Bit 18 – ECC Support RAM error correction.
Bit 17 – BinaryField Support binary field.
Bit 16 – PrimeField Support prime field.
Bits 15:12 – NbMult[3:0] Number of multipliers: 0x0: 1 multiplier 0x1: 4 multipliers 0x2: 16 multipliers 0x4: 64 multipliers 0x8: 256 multipliers
Bits 11:0 – MaxOpSize[11:0] Maximum operand size (number of bytes).
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