43.8.53 STATUS Register.

Table 43-54. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	PK_Registers__Status
Offset:	0x1200C
Reset:	0x00000000
Property:	R


Bit	31	30	29	28	27	26	25	24
				FailPtr[4:0]
Access				R	R	R	R	R
Reset				0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
							IntrptStatus	PK_Busy
Access							R	R
Reset							0	0


Bit	15	14	13	12	11	10	9	8
	ErrorFlags[11:4]
Access	R	R	R	R	R	R	R	R
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	ErrorFlags[3:0]
Access	R	R	R	R
Reset	0	0	0	0

Bits 28:24 – FailPtr[4:0] These bits indicate which data location generated the error flag. They are not available for all error flags.

Bit 17 – IntrptStatus This bit reflects the IRQ output value. It is set when the operation is finished. It is cleared when the CPU writes the bit 1 of Control Register.

Bit 16 – PK_Busy This bit reflects the BUSY output value. It is set when the operation starts and it is cleared when the operation is finished.

Bits 15:4 – ErrorFlags[11:0] These bits indicate an error condition. They are updated at the end of the operation. They are cleared when starting a new operation.

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