43.8.44 Sample clock divider.

Table 43-45. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	RNG_Control_Registers__ClkDiv
Offset:	0x11044
Reset:	0x00000000
Property:	RW

Bits 7:0 – ClkDiv[7:0] Sample clock divider. The frequency at which the outputs of the rings are sampled is given by: Fs=Fpclk/(ClkDiv+1).