12.4.3 FIFO Control Register (FCR)
Rx and Tx FIFOs are 16 bytes deep.
| Bit Number | Name | R/W | Default State | Description |
|---|---|---|---|---|
| [7:6] | RX_TRIG | W | 0b11 | These bits are used to set the trigger level for the Rx FIFO interrupt. Rx FIFO trigger level (bytes) are: 0b00: 1 byte 0b01: 4 bytes 0b10: 8 bytes 0b11: 14 bytes |
| [5:4] | Reserved | W | 0 | Software must not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit must be preserved across a read-modify-write operation. |
| 3 | ENABLE_TXRDY_RXRDY | W | 0 | Software must always set this bit to 1 for efficient data transfer from transmit FIFO to PDMA. |
| 2 | CLEAR_TX_FIFO | W | 0 | Clears all bytes in the Tx FIFO and resets its counter logic. The shift register is not cleared. 0: Disabled (default) 1: Enabled |
| 1 | CLEAR_RX_FIFO | W | 0 | Clears all bytes in Rx FIFO and resets counter logic. This shift register is not cleared. 0: Disabled (default) 1: Enabled |
| 0 | ENABLE_TX_RX_FIFO | W | 1 | It enables both the Tx and Rx FIFOs and is hardwired to 1, which means it is always enabled and cannot be changed. |