12.4.13 Modem Status Register (MSR)
| Bit Number | Name | R/W | Reset Value | Description |
|---|---|---|---|---|
| 7 | DCD | R | 0 | Data carrier detect (DCD) (MMUART_x_DCD).The complement of DCD input. When bit 4 of the Table 12-18 is set to 1 (loop), this bit is equivalent to OUT2 in the Table 12-18. |
| 6 | RI | R | 0 | Ring indicator (RI) (MMUART_x_RI). The complement of the RI input. When bit 4 of the Table 12-18 is set to 1 (loop), this bit is equivalent to OUT1 in the Table 12-18. |
| 5 | DSR | R | 0 | Data set ready (DSR) (MMUART_x_DSR). The complement of the DSR input. When bit 4 of the Table 12-18 is set to 1 (loop), this bit is equivalent to RTS in the Table 12-18. |
| 4 | CTS | R | 0 | Clear to send (CTS) (MMUART_x_CTS). The complement of the CTS input. When bit 4 of the Table 12-18 is set to 1 (loop), this bit is equivalent to DTR in the Table 12-18. |
| 3 | DDCD | R | 0 | Delta data carrier detect (DDCD) indicator. Indicates that DCD input has changed state. Whenever bit 0, 1, 2, or 3 is set to 1, a modem status interrupt is generated. |
| 2 | TERI | R | 0 | Trailing edge of ring indicator (TERI) detector. Indicates that RI input has changed from 0 to 1. Whenever bit 0, 1, 2, or 3 is set to 1, a modem status interrupt is generated. |
| 1 | DDSR | R | 0 | Delta data set ready (DDSR) indicator. Indicates that the DSRn input has changed state since the last time it was read by the Cortex-M3 processor. Whenever bit 0, 1, 2, or 3 is set to 1, a modem status interrupt is generated. |
| 0 | DCTS | R | 0 | Delta clear to send (DCTS) indicator. Indicates that the CTSn input has changed state since the last time it was read by the Cortex-M3 processor. Whenever bit 0, 1, 2, or 3 is set to 1, a modem status interrupt is generated. |