12.4.18 Glitch Filter Register (GFR)
| Bit Number | Name | R/W | Reset Value | Description |
|---|---|---|---|---|
| [7:3] | Reserved | R/W | Reserved | Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. |
| [2:0] | GLR | R/W | 0 | The glitch filter resynchronizes (GLR) and suppresses random input noise from MMUART_x_RXD (serial input data) and MMUART_x_SCK_IN (serial input clock in synchronous mode) based on the filter length given in number system clock cycles. The following are the different filter lengths in the APB clock cycles that can be written into the GLR register and their description. 0b000: Two resynchronize flip-flops are used but there is no spike suppression. 0b001: Three resynchronize flip-flops are used but there is no spike suppression. 0b010: Three resynchronize flip-flops are used and it also causes 1 APB clock cycle suppression. 0b011: Three resynchronize flip-flops are used and it also causes 2 APB clock cycle suppression. 0b100: Three resynchronize flip-flops are used and it also causes 3 APB clock cycle suppression. 0b101: Three resynchronize flip-flops are used and it also causes 4 APB clock cycle suppression. 0b110: Three resynchronize flip-flops are used and it also causes 5 APB clock cycle suppression. 0b111: Three resynchronize flip-flops are used and it also causes 6 APB clock cycle suppression. |