12.4.6 Interrupt Enable Register (IER)
| Bit Number | Name | R/W | Reset Value | Description |
|---|---|---|---|---|
| [7:4] | Reserved | R/W | 0 | Software must not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit must be preserved across a read-modify-write operation. |
| 3 | EDSSI | R/W | 0 | Modem status interrupt enable 0: Disabled (default) 1: Enabled |
| 2 | ELSI | R/W | 0 | Receiver line status interrupt enable 0: Disabled (default) 1: Enabled |
| 1 | ETBEI | R/W | 0 | Transmitter holding register empty interrupt enable 0: Disabled (default) 1: Enabled |
| 0 | ERBFI | R/W | 0 | Enables received data available interrupt 0: Disabled (default) 1: Enabled |