| [7:0] |
RBR |
R |
N/A |
This register holds the receive data bits for
MMUART_x. The default value is unknown as the register is loaded with data in
the receive FIFO. Bit 0 is the LSB and it is the first bit received. It might
be configured as the MSB by configuring the E_MSB_RX bit in the MM1. The
divisor latch access bit (DLAB), bit 7 of LCR, must be 0 to read this register.
This register is read only. Writing to this register with the DLAB 0 changes
the transmit holding register (Table 12-6) register value. |
