12.4.2 Transmit Holding Register (THR)
| Bit Number | Name | R/W | Reset Value | Description |
|---|---|---|---|---|
| [7:0] | THR | W | N/A | This register holds the data bits to be transmitted. Bit 0 is the LSB and is transmitted first. The MSB might be transmitted first, if it is configured with the E_MSB_TX bit in the MM1. The reset value is unknown as the register is loaded with data in the transmit FIFO. The DLAB, bit 7 of LCR, must be 0 to write to this register. This register is write only. Reading from this register with the DLAB 0 reads the Table 12-5 register value. |