10.1.9.1.5 Pseudo Random Counter

A Pseudo Random Counter is available using a Linear Feedback Shift Register (LFSR) architecture. The LFSR offers an efficient architecture for building very fast Pseudo Random Counters.

Figure 10-11. Generic Random Counter Architecture
þÿ

The Pseudo Random core architecture core is a simple shift register chain that uses two taps (one logic level) for the following widths: 2-7, 9-11, 15, 17, 18, 20-23, 25, 28, 29 and 31. The PRNG core uses five taps (three logic levels) for the following widths: 8, 12-14, 16, 19, 24, 26, 27, 30 and 32. The five-tap architecture operates slower than the two-tap implementation.